1. Field of the Invention
This application relates to an electrically rewritable and non-volatile semiconductor memory device and a method of using the same.
2. Description of the Related Art
Document 1: "SINGLE TRANSISTOR ELECTRICALLY PROGRAMMABLE MEMORY DEVICE AND METHOD", U.S. Pat. No. 4,698,787 (Oct. 6, 1987),
Document 2: "FLASH EEPROM ARRAY WITH NEGATIVE GATE VOLTAGE ERASE OPERATION", U.S. Pat. No. 5,077,691 (Dec. 31, 1991),
Document 3: "NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE", JP-A-3-219496,
Document 4: "CIRCUIT AND METHOD FOR ERASING EEPROM MEMORY ARRAYS TO PREVENT OVER-ERASED CELLS", U.S. Pat. No. 5,122,985 (Jun. 16, 192), and
Document 5: "A NOVEL CELL STRUCTURE SUITABLE FOR A 3 VOLT OPERATION, SECTOR ERASE FLASH MEMORY", IEDM 92-599-602, 1992.
As non-volatile semiconductor memory devices, an ultraviolet erasable type EPROM (Erasable and Programmable Read Only Memory) and an electrically and erasable (hereinafter referred to as "electrically alterable") EEPROM (Electrically Erasable and Programmable Read Only Memory) are well known heretofore, while recently an electrically flash EEPROM is developed.
More particularly, data stored in memory cells of the EPROM can be erased only by ultraviolet rays and can not be erased electrically. Accordingly, the EPROM requires a package with a transparent window. Further, in order to alter the stored data in the EPROM after mounting the EPROM on a board of a system, the EPROM must be disadvantageously removed from the board once. On the other hand, the EEPROM can be altered in a system, while generally the EEPROM has memory cells each requiring transistors for selection and separation and a channel area and accordingly there is a problem that an area of a memory cell thereof is about two times larger than that of the EPROM. Thus, in order to solve the problems, a flash type EEPROM capable of being electrically erased and having a memory cell area which is substantially equal to that of the EPROM has been developed.
The flash type EEPROM proposed in the early stage is described in the document 1, for example. This document discloses a method and a device structure for performing electrical writing and erasing by means of a single memory transistor having a floating gate. More particularly, in the erasing operation, a high voltage of 10 to 20 V is applied to a source terminal of a memory cell and a ground potential is applied to a control gate terminal to thereby generate a high electrical field in a thin insulating layer between a floating gate and the source terminal so that electrons are emitted from the floating gate by Fowler-Nordheim tunneling (hereinafter referred to as "FN injection") to thereby lower a threshold voltage of the memory cell as viewed from the control gate. On the other hand, in the writing operation, by applying a voltage of 5 to 10 V to a drain terminal of the memory cell and a high voltage of 10 to 15 V to the control gate and connecting a source to the ground, a strong inversion area is formed in a surface of a substrate between the drain and the source to generate hot electrons, so that electrons is injected into the floating gate (hereinafter referred to as "HE injection") to thereby raise the threshold voltage of the memory cell.
Further, the document 2 discloses a method in which the writing operation is the same as that of the document 1 and in the erasing operation by applying a negative voltage of -12 to -17 V to a control gate and connecting a source to the ground, electrons are pulled out from the floating gate by the FN injection. This method is improved as compared with the method of the document 1 in that a high voltage is not applied to the source in the erasing operation to thereby reduce a leakage current generated from the source in the erasing operation and further application of the negative voltage can be switched in a unit of row line by simplifying the generation of a high positive voltage and by connecting the control gates to a row line to perform decoding, so that erasing in a unit of selected row line can be attained instead of the flash type erasing.
Further, the document 3 discloses that, in addition to the method disclosed in the document 2, by applying a negative voltage of about -7 V to a control gate and a voltage of about 5 to 0 V to a drain and connecting a source to the ground in the erasing operation, erasing in a unit of bit can be attained by the FN injection, and in the writing operation by applying a high voltage of about 10 V to the control gate, a voltage of about 4 V to the source and a voltage of 0 V to the drain or making the drain open, writing in a unit of bit can be attained by the HE injection.
All of the methods disclosed in the above documents utilize the HE injection in the writing operation and the FN injection in the erasing operation although the applied voltages are different.
On the other hand, U.S. patent application Ser. No. 08/050,660, filed on Apr. 22, 1993, entitled "METHOD OF ALTERING A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE" or the document 5 discloses a method in which in the erasing operation by applying a high voltage of about 7 to 10 V to a control gate and a negative voltage of about -7 to -10 V to a substrate, a drain and a source, electrons are injected from a surface of the substrate into a floating gate by the FN injection to increase a threshold voltage of a memory cell. This method can attain erasing in a unit of row line. Further, in the writing operation, by applying a negative voltage of about -6 to -10 V to the control gate and a voltage of about 5 to 0 V to the drain, electrons are pulled out from the floating gate to the drain by the FN injection. Thus, by connecting the drain to a column line, writing in a unit of bit can be attained. This method is featured by a single memory transistor and utilization of the FN injection for both the erasing and writing.
Generally, the merit of utilizing the FN injection in the writing and erasing operation resides in no necessity of conducting a large current between a drain and a source of a memory cell for injection or discharge of electrons to the floating gate, a low power consumption in the writing operation because of a reduced current required for the FN injection, no necessity of providing an external power terminal for a high voltage or a negative voltage even if the high or negative voltage is required and a charge pump circuit provided in a memory device to be able to supply the voltage. On the other hand, a drawback thereof is that a writing speed is slow as compared with the HE injection (for example, about 10 .mu.s per bit for the HE injection, while about 1 ms for the FN injection).
On the contrary, in the HE injection, a time required for the writing and erasing operation is relatively short, while since it is necessary to conduct a large current between a drain and a source of a memory cell in the injection, there is a drawback that a consumption current becomes large (for example, a current between the drain and the source in the HE injection is about 1 mA per bit, while it is smaller than about 1 .mu.A in the FN injection).